With the development of communication technologies, users impose higher and higher requirements on the Quality of Service (QoS) such as capacity and speed of communication. The access network is one of the most technically challenging areas in the whole telecom network. In order to meet users' increasing requirements on the bandwidth and realize high speed, broadband, and intelligence of the access network, access technologies are emerging, such as Local Area Network (LAN), Digital Subscriber Line (DSL), Hybrid Fiber Coax (HFC) cable network, HFC-Cable modem, and Power Line Communication (PLC). However, the optical access technology is regarded as the most promising access technology. Passive Optical Network (PON) is an optical access trendsetter due to its easy maintainability, high bandwidth, and low costs, and is an ideal physical platform for accessing multiple services such as voice, data, and video services through a single platform.
The PON technology is a point-to-multipoint fiber access technology. A PON is composed of Optical Line Terminal (OLT), Optical Network Unit (ONU), and Optical Distribution Network (ODN). The Ethernet Passive Optical Network (EPON) technology is a good access technology. The EPON is characterized by easy maintenance, cost efficiency, high transmission bandwidth, and a high performance-to-price ratio. Especially, the EPON technology provides 1-10 GHz bandwidth, which enables simultaneous transmission of voice, data, and video services.
The EPON is a technology based on passive optical transmission, and involves no component of the amplification or relay function. Therefore, the transmission distance and the number of branches of the EPON depend on power budget and various transmission losses. With the increase of the transmission distance or the number of branches, the Signal to Noise Ratio (SNR) of the transmitted data diminishes, and more bit errors occur. In order to solve the problem, an FEC technology is introduced into the EPON system to improve the anti-interference capability of the system and increase the power budget of the system.
FEC refers to processing the signal in a specific mode before the signal is transmitted, and decoding the signal at the receiver end according to the corresponding algorithm to find and correct the erroneous codes. The basic working principles of the FEC in the EPON system are: An FEC check codeword is added after the Ethernet frame transmitted at the transmitter. The check codeword is correlated with the checked Ethernet frame data based on a determined rule. The receiver checks the relation between the Ethernet frame data and the check codeword according to the established rule. Once the transmission is erroneous, the relation is damaged, and the erroneous code is found and corrected automatically. The FEC technology strives to use the least check bytes to correct the most errors, and find the best tradeoff between the overhead (increased check bytes) and the obtained coding gain.
FIG. 1 shows a mapping relation between the Open System Interconnection (OSI) reference model and the IEEE802.3 LAN model. The model is applicable to the Ethernet defined by the 802.3-2005 standard. Currently, the 1 G and 10 G EPON systems employ such a model. Not only the FEC technology but also a line coding technology is introduced into the physical layer of the EPON system.
Line coding mechanisms are of two types: value mapping mechanism and scrambler mechanism. In the existing EPON system, the 8 B/10 B (B: Bit) line coding mechanism is applied, which is a value mapping mechanism. A significant drawback of the 8 B/10 B coding scheme is that the coding redundancy is up to 25%, and the coding overhead is great. In order to save the coding overhead, a series of standards such as 10 GBASE-W and 10 GBASE-R use the 64 B/66 B line coding on the Physical Coding Sublayer (PCS). In the 10 GBASE-T standard, the 64 B/65 B line coding is applied on the PCS. In the 10 GEPON system currently under development by the IEEE802.3av workgroup, the line coding mechanisms such as 64 B/66 B and 64 B/65 B of higher coding efficiency are introduced. The two line coding mechanisms use the scrambling mode that carries non-scrambled synchronization characters and control characters.
The 64 B/66 B coding mechanism adds a 2-bit synchronization character (synchronization header) on the basis of the 64-bit information. The 2-bit synchronization character is arranged in either of the two modes: “01”, or “10”. The synchronization character “01” means that all the 64 bits are data information; the synchronization character “10” means that the 64 bits include data information and control information. The synchronization character “00” or “11” means that errors occur in the transmission process. Meanwhile, the use of the synchronization character ensures that the transmitted data has at least one “0” and “1” transition at intervals of 66 bits, which facilitates the implementation of Block Synchronization (BS). The 64-bit information is scrambled through an auto sync scrambling mechanism, thus maximally ensuring enough changeover of all transmitted information and facilitating clock recovery at the receiver end. Compared with the 64 B/66 B coding mechanism, the 64 B/65 B coding uses a 1-bit data/control character. The data/control character “0” means that all the 64 bits are data information; the data/control character “1” means that the 64 bits include data information and control information.
Currently, a design scheme pertinent to the PCS in a 10 G EPON system is shown in FIG. 2 and FIG. 3. FIG. 2 is a transmitting flowchart on the physical layer of this system; and FIG. 3 is a receiving flowchart on the physical layer of this system.
In FIG. 2, the Ethernet data frame is processed by a reconciliation sublayer and a 10 Gigabit Media Independent Interface (XGMII) first, and then undergoes the 64 B/66 B line coding. The coding process is to add a 2-bit synchronization character to the 64-bit Ethernet data information so that the data changes from 64 bits to 66 bits. Generally, the encoded 66-bit codeword is called a block. Subsequently, the data and the control information in the block are scrambled, and then the data in the frame undergoes FEC coding. The encoded data passes through the Physical Medium Attachment (PMA) sublayer and the Physical Medium Dependent (PMD) sublayer, and is then sent out. The receiving process on the physical layer is an inverse of the sending process, as shown in FIG. 3.
In the process of research and practice, the inventor finds that the line coding and the FEC coding bring benefits at the cost of increasing redundant information. In the prior art, the data that has undergone the line coding and the FEC coding is framed and sent directly; if the algorithm selected in the line coding involves high redundancy, then a large amount of redundant information is encoded as the data part of the FEC coding, this affects the performance of the FEC coding; if the algorithm selected in the line coding involves low redundancy, the FEC performance is improved but the synchronization performance of the transmission system is affected. It is hard to accomplish a tradeoff between them.